It is generally known to install watchdog circuits in microprocessor circuit arrangements to monitor the program flow for the processor. When the programs run correctly, the microprocessor triggers the watchdog circuit in specific time intervals. This enables the microprocessor's program flow to continue without hindrance. If there is a malfunction, however, for example because the microprocessor "gets hung up", the watchdog circuit is no longer triggered. This induces the watchdog circuit to emit a reset pulse which is then fed to the microprocessor. By this means, the microprocessor is reset to the program start or to a predetermined point in the program (reset function).
U.S. Pat. No. 4,803,682 discloses a microprocessor circuit arrangement with a watchdog circuit that monitors the correct processor program flow. An additional reset signal is generated when transmission errors occur in succession between a first microprocessor circuit and other subordinate microprocessor circuits, whereby all the microprocessor circuits are connected by means of a mutual transmission line. If one of the reset signals appears, the multitude of subordinate microprocessor circuits is reset.
In the case of the monitoring watchdog circuit according to the publication, Patent Abstracts of Japan, vol. 8, no. 60 (P-262) (1497), Mar. 22, 1984 & JP-A-58 211 255, the watchdog circuit is designed as a special microcomputer, which resets other microcomputers, in case they continue to run without emitting specific pulse sequences within a specific period of time at their output.
In addition, U.S. Pat. No. 4,586,179 discloses a voltage-level monitoring, which resets the microprocessor in case the input voltage falls under a certain value. A starting-curring monitoring, which is coupled between the voltage-level monitoring and the watchdog circuit, guarantees that a subsequently added reset-trigger switch keeps the microprocessor in the reset state, until the input voltage reaches a certain level, which allows a normal microprocessor operation.
Finally, the data processing system according to the publication EP-A-O 266 837 contains a clocked counter as a watchdog timer, whose first output is coupled to a reset input of the microcomputer. To increase the number of malfunctions which the watchdog circuit reacts to, the microcomputer is equipped to repeatedly generate reset-signal bytes within a certain timing window, whereby these timing windows correspond to periods of time during which another output of the counter is set to logic "1". However, such malfunctions can only be recognized when the entire data processing system is in the write mode. The microcomputer is reset in this write mode, when a byte output by the microprocessor does not conform to a byte stored, for example, in the RAM. Thus, the microprocessor is prevented from mistakenly running through a program part, in which relevant storage locations are then overwritten. In this case, an additional reset signal is automatically generated for the microcomputer.